The invention relates to a semiconductor device, and more particularly, to a method for fabricating an inter dielectric layer in a semiconductor device.
With development of semiconductor device fabrication technology, the critical dimension (CD) of bit line stacks is rapidly decreasing. As the CD of the bit line stacks decreases, a space defined between the bit line stacks also decreases. Therefore, there is a limitation in a high density plasma (HDP) process used as a gap filling method. One example is a bending phenomenon in which a bit line stack becomes bent.
FIG. 1 illustrates a cross-sectional view of a conventional bit line stack, FIG. 2 illustrates a scanning electron micrograph (SEM) of bit lines having a high aspect ratio, and FIG. 3 illustrates a SEM of a defect in which a storage node contact is not formed.
Referring to FIG. 1, bit line stacks 120, including barrier metal patterns 105, conductive patterns 110, and hard mask patterns 115, are formed on a semiconductor substrate 100, and an interlayer dielectric layer 125 is formed to fill the areas surrounding the bit line stacks 120. The interlayer dielectric layer 125 is formed using an HDP process. However, when the interlayer dielectric layer is formed using the HDP process, a bending phenomenon may occur so that a given bit line stack 120 is bent. The bending phenomenon may occur when unequal attraction is applied to one of the bit stacks 120 by a difference in an amount of charges applied to the left and right side of the bit line stack 120 due to plasma generated during the HDP process, or it may occur as a result of a damage caused by plasma. Due to limitations of the fabricating process, a bit line stack in a 50 nm device is filled using a flowable layer. Although the flowable layer was developed as a material for device isolation, many studies have been conducted to use the flowable layer in a process requiring a gap fill, such as an isolation layer a gate stack, or a bit line stack.
However, the bending phenomenon occurs even though the gap fill process is performed using the flowable layer. As illustrated in FIG. 2, the bit line stacks 120 have a large aspect ratio (i.e., height to width ratio), and the flowable layer is softer than an HDP oxide layer. Therefore, when the flowable layer is used, it does not endure a subsequent thermal process and a self align contact (SAC) process, and the bit line stacks 120 may be bent to one side due to an unequal attraction. When a subsequent process is performed and the bit line stack 120 is bent in one direction, a storage node contact hole 300 may not be formed, as indicated by a reference symbol “A” in FIG. 3.